Conventional anti-fuse memory cells are disclosed in U.S. Pat. No. 6,822,888 (patent literature 1) and Japanese Patent Publication (JP 2007-80302A; patent literature 2).
FIG. 1 shows a circuit configuration of a conventional anti-fuse memory cell disclosed in U.S. Pat. No. 6,822,888. The anti-fuse memory cell is arranged in a matrix. A plurality of word lines Vwr1 (SR), Vwr2 (UR), . . . , and a plurality of counter lines Vwp1 (SR), Vwp2 (UR), . . . , are connected to rows of a memory cell array, respectively. A plurality of bit lines Vb1 (SC), Vb2 (UC), . . . are connected thereto columns of the memory cell array, respectively.
The anti-fuse memory cell has one N-type MOS (Metal Oxide Semiconductor) transistor and one anti-fuse element. The anti-fuse element has first and second electrodes. The anti-fuse element is composed of an N-type MOS transistor and has a gate oxide film. For example, in a first anti-fuse memory cell, the N-type MOS transistor is connected between the bit line Vb1 (SC) and the first electrode of the anti-fuse element, and the gate is connected to the word line Vwr1 (SR). The second electrode of the anti-fuse element is connected to the counter line Vwp1 (SR). In a second anti-fuse memory cell, the N-type MOS transistor is connected between the bit line Vb1 (SC) and the first electrode of the anti-fuse element and the gate is connected to the word line Vwr2 (UR). The second electrode of the anti-fuse element is connected to the counter line Vwp2 (UR).
Citation List:
                Patent literature 1: U.S. Pat. No. 6,822,888        Patent literature 2: JP 2007-80302A        Patent literature 3: JP 2000-299383A        